The prior art contains many general references relating to the handling of addresses and data which disclose circular addressing circuitry or systems.
In U.S. Pat. No. 4,202,035, filed on Nov. 25, 1977, there is disclosed modulo addressing apparatus which includes an adder having its output connected to the input of a modulo addition logic unit with a multiplexer (MUX) also being connected to the inputs of the modulo addition logic unit as well as to the inputs of the adder to provide a random access memory (RAM) address at the output of the modulo addition logic unit.
Circular addressing circuitry is disclosed in an IBM Technical Disclosure Bulletin article, "Circular Addressing Circuitry For Accessing Computer Storage", by G. H. Hatfield, A. Peled and R. H. Riekert, Vol. 20, No. 2 July 1977, pp. 871-872, wherein outputs from an adder and a mask register are fed into a first AND circuit which has its output combined with the output of a second AND circuit to provide an effective address through an OR circuit.
U.S. Pat. No. 3,980,874, filed on May 9, 1975, by C. R. Vora, discloses apparatus for translating to modulo M a binary number of value greater than a number M.
Commonly assigned U.S. Pat. No. 4,569,016, filed on June 30, 1983, by H. T. Hao, P. W. Markstein and G. Radin, discloses a mechanism for performing mask and rotate instructions.
In general, the approach to implementing circular addressing is to suppress the carry in the carry chain of an adder at a predetermined modulo boundary. Two concerns exist with this approach. First, extra stages of delay are added at each modulo boundary area and, second, logically negative modulo addressing cannot be performed.